[PDF] Insertion and promotion for tree-based PseudoLRU last-level caches | Semantic Scholar (2024)

This work proposes old Tree-based PLRU on two-level caches with higher speed up or performance matching of LRU at GPUs with high accuracy profiling logic and cache partitioning hardware for this scheme.

Value based Insertion Policy (VIP) is proposed which aims to reserve more blocks with higher values in the cache which can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead.

This paper proposes a method that uses a buffer called the history queue to record longer-term access-eviction patterns than the LRU buffer can capture, and makes a simple modification to LRU insertion policy such that recently-recalled blocks have priority over others.

It is found that a simple replacement policy with minimal overhead provides at least the same benefit as a state-of-the-art replacement policy in the presence of aggressive pattern-based prefetching.

This thesis proposes two cache management techniques, one domain-agnostic and onedomain-specialized, to improve cache efficiency by addressing variability in reuse prediction and aims to design robust cache management mechanisms and policies for LLC in the face of variability in reused blocks.

This paper proposes a holistic cache management technique called Kill-the-PC (KPC) that overcomes the weaknesses of traditional prefetching and replacement policy algorithms and removes the need to propagate the PC through entire on-chip cache hierarchy while providing a holistic caches management approach with better performance.

This paper proposes a control system to dynamically optimize the history partitions and the cache allocation priorities at the same time by using the statistics of the history structure and indicates that the proposed technique improves performance considerably compared with the conventional LRU-based approach and others.

Three novel cache replacement policies for L2 cache that are targeted towards parallel multi-threaded applications that generate differing patterns of workload at different intervals are proposed and offer an improvement of up to 9% in overall hits at the L1 cache level and an IPC speedup of 1.08 times that of LRU for a wide range of multithreaded benchmarks.

The results show that state-of-the-art prefetchers are fundamental when evaluating replacement policies due to their tight interplay, and that inclusive caches require a less aggressive prefetching mechanism to prevent excessive back-invalidation.

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This work uses decision tree analysis of multi-set-dueling to choose the optimal insertion position in the LRU stack, which reduces misses by 5.16% and achieves 7.19% IPC improvement over LRU.

A Dynamic Insertion Policy (DIP) is proposed to choose between BIP and the traditional LRU policy depending on which policy incurs fewer misses, and shows that DIP reduces the average MPKI of the baseline 1MB 16-way L2 cache by 21%, bridging two-thirds of the gap between LRU and OPT.

A new counter-based approach to deal with cache pollution, predicting lines that have become dead and replacing them early from the L2 cache and identifying never-reaccessed lines, which is augmented with an event counter that is incremented when an event of interest such as certain cache accesses occurs.

This work proposes to directly predict reuse-distances via instruction-based (PC) prediction and use this information for cache level optimizations and evaluates the reusedistance based replacement policy of the L2 cache using a subset of the most memory intensive SPEC2000.

A new way to use dynamic reuse distances to further improve cache management policies is proposed which prevents replacing a cache line until a certain number of accesses to its cache set, called a Protecting Distance (PD).

Evaluations with the SPEC CPU2000 benchmarks show that MLP-aware cache replacement can improve performance by as much as 23% and a novel, low-hardware overhead mechanism called sampling based adaptive replacement (SBAR) is proposed, to dynamically choose between an MLp-aware and a traditional replacement policy, depending on which one is more effective at reducing the number of memory related stalls.

This paper introduces sampling dead block prediction, a technique that samples program counters (PCs) to determine when a cache block is likely to be dead, and shows how this technique can reduce the number of LLC misses over LRU and be used to significantly improve a cache with a default random replacement policy.

This work proposes a new cache management approach that combines dynamic insertion and promotion policies to provide the benefits of cache partitioning, adaptive insertion, and capacity stealing all with a single mechanism.

This paper proposes a new class of dead-block predictors that predict dead blocks based on bursts of accesses to a cache block, and evaluates three ways to increase cache efficiency by eliminating dead blocks early: replacement optimization, bypassing, and prefetching.

The zcache is presented, a cache design that allows much higher associativity than the number of physical ways, and it is shown that zcaches provide higher performance and better energy efficiency than conventional caches without incurring the overheads of designs with a large number of ways.

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